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Education

M.E. in Electronics Engineering
Major in Electromagnetic Fields and Microwave Technology
Shanghai Jiao Tong University
09/1999 - 03/2002

B.E. in Electronics Engineering
Major in Communication Engineering
Shanghai Jiao Tong University
09/1996 - 07/1999

Work Experience

2005.7 - Present
Senior IC Development Engineer
NXP Semiconductors (Former Philips Semiconductor), BL Cellular Systems, MST Baseband - Shanghai, China

• Developed a digital baseband chip containing ARM946 and R.E.A.L DSP. The chip was fabricated in a 90nm process with the first tape-out in December, 2006.
• Co-submitted a Patent Draft.
• Responsible for the entire design synthesis flow, netlist screening and formal verification.
• Participated in PNX6511 risk assessment and tracking.
• Integrated DSP Firmcore into design database and updated corresponding testcases.
• Responsible for DSP supplier agreement management.
• Developed an ARM7 based digital baseband chip from July 2005 to January 2006. The project was stopped due to business reason.
• Translated timing constraints from PKS TCL to SDC and verified the constraints.
• Set up clock tree synthesis flow and wrote clock tree synthesis constraints.
• Set up PrimeTime environment and performed static timing analysis.
• Received training in backend design in Zurich, Switzerland.

04/2002.4 - 06/2005
Technical Support Engineer
Shanghai Research Center for IC Design, Multi-Project Wafer Department - Shanghai, China

• Provided customer support for RTL-to-GDS flow.
• Provided designers with manufacturing support on multiple processes, including CSMC 0.6um DPDM logic, Chartered 0.35um logic/analog/RF and SMIC 0.35um e-EEPROM process.
• Developed a PIC16C84 compatible MCU, from specification to tape-out. Test chip was fabricated at Chartered 0.35um logic process and first-time right.
• Participated in multiple customers' design projects. Work packages included synthesis, static timing analysis, RTL coding, FPGA emulation platform set-up and functional verification. Some of the chips are in mass-production.
• Documented internal digital design flow of CSMC 0.6um logic process and TSMC 0.25um logic process.

Publications

Chenbo Liu, Zhengfan Li, "Parameter Extraction for Capacitance of On-Chip Interconnects", in the Journal of Shanghai Jiao Tong University, Vol.37 No.3, Shanghai, China, March, 2003, pp. 380-382.

Chenbo Liu, Yuyang Wang, Zhengfan Li, "Frequency-Dependent Parameter Extraction for Distributed Resistance and Inductance of On-Chip Interconnects", in the Journal of Microwaves, Vol.18 No.2, Nanjing, China, June, 2002, pp. 9-13,32.

Yuyang Wang, Chenbo Liu, Zhengfan Li, "Programming of Resistance and Inductance Frequency-Dependent Parameter Extraction of IC Interconnection Line: in the Journal of Shanghai Jiao Tong University, Vol.36 No.6, Shanghai, China, June, 2002, pp. 830-832.

Chenbo Liu, "Electrical Performance Analysis of On-Chip Interconnect for High Speed Integrated Circuits", Master Thesis, Shanghai, China, January, 2002.

Chenbo Liu, Zhengfan Li, "Conductor Cross-Section Moment Method Applied in IC Interconnects Resistive and Inductance Parameter Extraction", in the Proceeding of 4th International Conference on ASIC, Shanghai, China, October, 2001, pp. 720-723.

Technical Skills

Programming Languages

• C/C++, Verilog HDL, Perl, C Shell, Korn Shell, Tcl

EDA Tools

• Synopsys Design Compiler, PrimeTime, Leda
• Cadence NC-Sim, Ambit BuildGates, RTL Compiler, Silicon Ensemble, Conformal, Dracula DRC
• Mentor Model-Sim, Calibre DRC

Operating Systems

• Windows 2000/XP, Solaris, Red Hat Linux

Honors

Membership

Reference

Available upon request.